Effects of RTA and WSi/sub x/-polycide gate processes on MOSFET reliability for giga-bit scale DRAMs

We report the process effects on the MOSFET reliability and characteristics for the gate stack formation process in DRAM (Dynamic Random Access Memory). A rapid thermal annealing (RTA) process, employed for the reduction of word-line resistance and the improvement of hot-carrier life-time, caused an increase of the gate-induced drain leakage (GIDL) current. WSi/sub x/ gate dependence, Hot-Carrier (HC) and Fowler-Nordheim (FN) stress effects are also studied.