An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield

We have developed two schemes for improving access speed and reliability of a loadless four-transistor (LL4T) SRAM cell: a dual-layered twisted bitline scheme, which reduces coupling capacitance between adjacent bitlines in order to achieve highspeed READ/WRITE operations, and a triple-well shield, which protects the memory cell from substrate noise and alpha particles. We incorporated these schemes in a high-performance 0.18-/spl mu/m-generation CMOS technology and fabricated a 16-Mb SRAM macro with a 2.18-/spl mu/m/sup 2/ memory cell. The macro size of the LL4T-SRAM is 56 mm/sup 2/, which is 30% to 40% smaller than a conventional six-transistor SRAM when compared with the same access speed. The developed macro functions at 500 MHz and has an access time of 2.0 ns. The standby current has been reduced to 25 /spl mu/A/Mb with a low-leakage nMOSFET in the memory cell.