17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter

This work presents a 12.5GHz fractional-N type-I sampling PLL achieving an rms jitter of 58.2fs (integrated from 1kHz to 100MHz) at 18mW power consumption and occupying an area of 0.16mm2. A 1b TDC with a simple digital phase-error-correction (DPEC) circuit is leveraged to simultaneously (i) limit the SPD phase error with no extra quantization noise and (ii) extract a digitized version of the phase error needed for the accurate cancellation of the fractional quantization error.