RTL Power Estimation: Early Design Cycle Approach for SoC Power Sign-Off

VLSI industry is driven by three main factors. They are Power, delay and area. In 180nm and 90nm days, IP (Intellectual Property) and SoC (System on Chip) designs were less complicated because of lower transistor density. As technology is miniaturizing, more number of transistors are packed within the same area. This further has impact on packaging and cooling requirements of the chip. Thus there exists necessity to estimate the power early in the design space exploration. Power evaluation is done immediately after RTL (Register Transfer Level) design is available so that packaging and cooling requirements are validated. Added advantage of estimating power early in the ASIC (Application Specific Integrated Circuits) flow is that the details of power distribution across various IPs in SoC can be analyzed. By proper analysis of power distribution, suitable power optimization techniques can be exercised to save power. All these factors motivate to estimate power after RTL design stage. In this paper, RTL power estimation flow for industrial design using Joules tool of Cadence is developed. RTL power numbers are estimated for different IPs and SoC maximum collate power is evaluated. RTL power numbers are validated by correlating the power numbers obtained after P & R stage by Voltus tool from Cadence. There will be expected mismatch in the power numbers between RTL and P & R stages, as RTL stage doesn't contain information pertaining to wires and interconnects. Results verify that RTL power numbers are within 5.007% accuracy loss with respect to P & R stage power numbers.