A 9-ns, 1.4-gigabyte/s, 17-ported CMOS register file

Advances in circuit and microarchitecture design have made it possible to develop a 9-ns, 17-ported register file which can support a full 1.4-gigabyte/s bandwidth. With 79000 transistors in a 1- mu m CHMOS process, the 4 K register file is a major unit of a microprocessor, which is a 100-MOPS VLSI parallel processing component with an integrated communication unit. The benefit of increased system performance is realized since all connected functional units can receive full bandwidth operand supply. A brief introduction gives a conceptual framework to understand the architecture and bandwidth implications. Various techniques were used to optimize the macroarchitecture by modifying the register file's internal microarchitecture. All aspects of the design including read/write circuitry, cell stability, and special access cells are described.<
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