Pipelining router design improves parallel system performance

Efficient communication on fetching remote data is a critical parameter in distributed shared-memory multiprocessors (DSM) in order to achieve high performance. Message passing techniques are used in many modern communication systems and routers are essential building blocks for these communication systems. Hence, in this paper emphasis is placed on the design of routers for 2-ary n-cube networks. Based on a simple deadlock free algorithm, we analyze the influence of the router structure. To be more precise, the parameters considered were the clock frequency and the number of pipeline stages of the router. The performance evaluation for DSM applications shows there are significant gains in using segmented routers designs, in our evaluations, results show an improvement of up to 12% in the execution time of some applications. This improvement occurs even though the base latency of the router has increased by 40%.