Hierarchical 3D-torus interconnection network

Three dimensional (3D) stacked implementation has been proposed as a new technology for massively parallel computers. However, two major limitations have hindered the progress in this direction: the technology of vertical interconnects and the cost in terms of area for these vertical interconnects. Each vertical interconnect requires 300 /spl mu/m/spl times/300 /spl mu/m area, thus liberal is prohibited. Clearly, an interconnection philosophy which minimizes these vertical links can contribute to the success of a 3D implementation. A hierarchical 3D-torus network, called H3D-torus has been proposed to reduce the number of vertical links in 3D stacked implementation but keeping good network feature. This paper addresses the architectural details of the H3D-torus network, and explores aspects such as the network diameter, the peak number of vertical links, and VLSI layout area for the H3D-torus network as well as for several commonly used networks for parallel computers.