FPGA Implementation of FBMC Baseband Modular for 5G Wireless Communication

In recent years research, selection in regard to a potential waveform successor for the fifth generation (5G) telecommunication systems has been focused. On a contrary with OFDM, Filter-bank Multicarrier (FBMC) modulation has been put forward as a next valid waveform to be used in 5G systems because to its finer spectral efficiency and reduced out-of-band emissions. As an outcome, baseband processors to be developed in hardware, as the current state of the work was done, evaluating former design proposals for instance Polyphase Network and Frequency Spreading FBMC Transmitter. Based on the research, architecture to be realized was chosen. The system technologically advanced on comparison with a prevailing software model using MATLAB. The reconfiguration, concise size, high computational power makes FPGA efficient in DSP applications. The developed work involves modelling and execution of FBMC baseband modulator and evaluates key metrics concerning performance, resource utilization and power consumption on FPGA. The proposed architecture is simulated and synthesized using Verilog HDL in Xilinx ISE Design Suite 12.1 and to be implemented on Spartan -3 XC3S50 FPGA board. The recommended structure can be progressed further to surge the complexity of the hardware structure as a result of which a reduced amount of resource could be used to model prototype hardware for the presented FBMC scheme.