Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits

This paper presents an overview of the SMART-LEES (Singapore MIT Alliance for Research and Technology - Low Energy Electronic Systems) research program that has been on-going in the past 8 years. The program is directed towards monolithic co-integration of III-V materials into Si-CMOS 200-mm foundry wafers in a single chip, which would open doors for many novel integrated circuit (IC) applications, including GaN and InGaAs high electron-mobility transistors (HEMTs), light-emitting diodes (LEDs), heterojunction bipolar transistors (HBTs), hybrid III-V/SI circuit components, as well as scalable radio-frequency (RF) compact models (CMs).