Evaluation of Partially Constant, Fine-Grained, Dynamic Partial Reconfigurable Functions in FPGAs

Dynamic Partial Reconfiguration (DPR) is a well-established technique for changing the functionality of a circuit in an FPGA during runtime. However, DPR can also be used to simplify any given function by replacing one or more inputs or parts of an input of a function by multiple versions of that function. During deployment, depending on the current value of the replaced inputs, a new partial configuration is programmed. This concept of decomposing digital circuits is known as Boole's expansion theorem (also known as Shannon's expansion theorem). Its feasibility in a DPR scheme is investigated in this work and required conditions for its application to fine-grained functions are identified. An extension of the Xilinx Vivado design flow is presented to facilitate the efficient generation of large numbers of partial configurations. The proposed DPR scheme is applied to fixed-point multiplication and division circuits in order to evaluate its performance. Resource utilization, power, and critical path latency are evaluated and compared with conventional FPGA implementations of the same circuits. It is found that the proposed DPR scheme allows for the reduction in power and in critical-path delay in certain scenarios.