A Practical Estimation of Periodic Power Supply Induced Jitter for Clock Buffer Chains

This paper presents a simple but practically accurate analytical closed-form expression for estimation of periodical power supply induced jitter (PSIJ) in MOS clock buffer chains. The closed-form expression is algebraically simple requiring only a few circuit simulation results without the pre-knowledge of circuit SPICE parameters. The expression predicts MOS clock buffer's period PSIJ and N-Cycle PSIJ. Compared to SPICE simulated jitter, the closed-form expression predicts PSIJ with a maximum +30% error, which is generally sufficient for early-stage clock-buffer jitter budgeting before circuit implementations. The expression can be hand calculated and is well suited for IC design and application engineers to quickly summarize jitter tolerances for clock distribution networks in high-speed PHYs such as DDRs and SERDESes.