Low power decimation filter design for /spl Delta/-/spl Sigma/ converters

This paper reports on a new low power implementation of a decimation filter with a two-path architecture. The filter reduces the power consumption by better than 50% over previous work. Instead of decimating data after filtering, the reported technique performs data division on the front end. As a result of the two-path architecture, the adder clocking as well as the number of additions is reduced. As a result of the reduction in the number of additions, overall power efficiency is increased by a factor of two. Moreover, the presented two-path filter has greater attenuation and a narrower transition band than an equivalent implementation of a sine filter, The elemental filter blocks were submitted for fabrication in IBM's 0.1 um thin film SOI CMOS process for delay power evaluation.