Timing-driven partitioning and timing optimization of mixed static-domino implementations

Domino logic is a circuit family that is well-suited to implementing high-speed circuits. Synthesis of domino circuits is more complex than static logic synthesis due to the noninverting nature of the logic and the complex timing relationships associated with the clock scheme. In this paper, we address several problems along a domino synthesis flow. We mainly consider the problem of partitioning a circuit into static and domino regions under timing constraints. The algorithm is extended to develop a method for partitioning domino logic into two phases, with inverters permitted between the two phases, and then to a flow for general two-phase static-domino partitioning. We also address a timing verification and sizing optimization tool for circuits containing mixed domino and static logic.