Fully depleted SOI devices with TiN gate and elevated source-drain structures

As microelectronics technology enters the deep-submicron arena, fully depleted SOI (FDSOI) technology assumes a prominent position as a potential solution to the problems associated with continued device scaling. Some of the possible benefits of using FDSOI are improved control of the transistor threshold voltage, lower junction capacitance, higher device packing density, and latchup immunity (Maiti et al, 1998). Fully depleted SOI devices with a metal gate (MGFDSOI) offer the additional benefits of eliminating polysilicon depletion, allowing thinner electrical gate dielectric thickness for the same physical thickness along with reduced gate sheet resistance (Colinge, 1997). For FDSOI structures with ultrathin (<200 /spl Aring/) superficial silicon thickness, epitaxially deposited Si is used to increase the available depth for silicidation in the source-drain areas. This technique, referred to as elevated source/drain (ESD), ensures lower contact resistance with the device. This paper reports the results of physical and electrical characterization of MGFDSOI device structures.