Hot electron lifetimes of partially-depleted 0.35 /spl mu/m SOI NMOS transistors

It has recently been proposed that bulk MOS devices with deep submicron gate lengths and/or at cold temperatures, have an increased tendency for the worst case hot electron condition to exist when V/sub gs/=V/sub ds/ (King et al, 2000; Rosenbaum et al, 1999; Wang-Ratkovic et al, 1999). This condition is different from the conventional DC stressing test at the peak substrate current proposed by Takeda and Suzuki and adopted as JEDEC standard (1997). This paper assesses the hot electron lifetime of radiation hard 0.35 /spl mu/m SOI NMOS transistors under both conditions at temperatures ranging from 77 K to 398 K. These SOI NMOS transistors are fabricated on radiation hardened standard SIMOX substrates.