A 0.5-1 V MTCMOS/SIMOX SRAM macro with multi-V/sub th/ memory cells

Summary form only given. Sub-1 V CMOS circuit technology on ultrathin-film SOI is the most effective candidate for ultralow-power applications in future ULSIs. We have proposed various multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuits (Douseki et al., 1996; Fujii et al., 1998) that operate at an ultralow supply voltage down to 0.5 V. Combining fully-depleted low-V/sub th/ CMOS logic gates and partially-depleted high-V/sub th/ power-switch transistors makes it possible to achieve high-speed and low-power operation in both the active and the sleep mode. Using MTCMOS/SIMOX technology, we have developed various sub-1 V digital LSIs (Douseki et al., 1998; Fujii et al., 1999). However, it has been difficult to apply MTCMOS/SIMOX technology to SRAM. This is because a memory cell has to be composed of high-V/sub th/ MOSFETs to store data in the sleep mode. The high-V/sub th/ cells and the read-out circuit around them disturb high-speed and low-power operation of the SRAMs. Low-voltage SOI memories (Shahidi et al., 1993; Shimomura et al., 1997) that operated at a supply voltage of around 1 V have been reported, but there are no ultralow-voltage memories that operate at supply voltages down to 0.5 V. In this paper, we describe a multi-V/sub th/ memory cell that performs high-speed read operation at low-V/sub th/ MOSFETs and a high-V/sub th/ charge-transfer-type multiplexer that makes possible high-speed and low-power operation for large capacity SRAMs with large bit-line capacitance.