Implementation of two dimensional forward DCT and inverse DCT using FPGA

This paper describes the (field programmable gate array) FPGA implementation of two dimensional forward and inverse discrete cosine transform (2D-DCT and 2D-IDCT) using the 100 K gate ALTERA FLEX10K100 FPGA/CPLD. The architecture used in both 2D-DCT and 2D-IDCT is based on the conventional row-column decomposition method. The use of a fast algorithm and distributed arithmetic (DA) technique to implement the DCT and IDCT greatly reduces the hardware complexity.