A hybrid VIGBT-LDMOS transistor

A hybrid VIGBT-LDMOS transistor which consists of a VIGBT (vertical insulated-gate bipolar transistor) path with a lateral DMOSFET path, implemented in a 300-V, p-channel version, has been demonstrated. The device can be operated with series resistors attached to either the collector or the drain terminals. The case in which the collector resistor equals zero is called the LACOSH-VIGBT (lateral collector shorted-vertical IGBT), and the case in which the drain resistor equals zero is called LABIENFET (lateral bipolar enhanced DMOSFET). Experimental characterization of the LACOS-VIGBT showed that the onset of the minority injection is retarded from 0.6 to 1.1 V, and the forward drop varies from 1.4 to 3.6 V and from 1.1 to 3.0 V, with and without the collector short, respectively, for 1 A (14 A/cm/sup 2/) to 6 A (83 A/cm/sup 2/) of collector current. Corresponding improvements in turnoff times are 5.5-4.4 mu s vs. 9.5-7.2 mu s. The reverse conducting diode has a forward drop of 0.82-1.57 V for 1-6 A of current and a switching time over 10 mu s. In the LABIENFET mode, the forward drop at 1 A (14 A/cm/sup 2/) decreases from 15.6 to 1.4 V when the collector series resistance changes from 150 to 0 Omega , with corresponding turnoff times of 1.7-5.5 mu s. This device is attractive either as a fast switching VIGBT or as a low-voltage-drop FET, with an integral antiparallel diode.<
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