Combinational Decompressors with Nonlinear Codes

Test patterns are transferred from the tester to the circuit under test in a compressed form as it minimizes test access mechanism bandwidth and transfer time. It was found that nonlinear binary codes could be useful for encoding test patterns in a similar way as linear ones and the compression efficiency may be higher. The key important characteristics of the nonlinear codes are that the number of codeword bits may be higher than it is for the linear code words while the number of specified bits is preserved. The nonlinear binary codes can be used in test pattern decompressors. It causes better encoding characteristics can be obtained for a higher number of parallel scan chains comparing with linear codes. In this paper, we propose a relatively fast heuristics that can be used for finding the nonlinear function truth tables guaranteeing the required number of specified bits and enables hardware overhead minimization. We quantify the benefits and costs of decompressors with nonlinear codes and verify the benchmark circuit test pattern encoding efficiency.