Built-in self-reconfiguring systems for mesh-connected processor arrays with spares on two rows/columns

The author discusses some reconfiguration methods where faulty PEs are compensated for by spare PEs located in two rows/columns in/around a mesh-connected array since they have the advantages that the numbers of spare PEs and the network overheads for reconstructions are relatively small. First, the author discusses how arrangements of spare PEs and network architectures affect the efficiencies of reconfigurations. As arrangements of spare PEs, he considers the cases where either spare linear arrays face each other or are located orthogonally. As replacements of faulty PEs by spare PEs, straight shifts using double or single tracks are considered. Reconfiguration algorithms are given for the proposed methods. The efficiencies of reconfigurations for the methods, that is, the reconfiguration probabilities, are compared with each other. Finally, the author presents built-in self-reconfiguring systems for the proposed methods by hardware. This implies that the proposed methods are effective in enhancing the run-time reliabilities as well as the fabrication-time yields of the processor arrays.