Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells

A 3/spl times/3-bit Coulomb blockade memory cell array has been fabricated in silicon-on-insulator (SOI) material. In each cell, the Coulomb blockade effect in a single-electron transistor is used to define two charge states. The charge is stored on a memory node of area 1 /spl mu/m/spl times/1 /spl mu/m or 1 /spl mu/m/spl times/70 nm and is sensed with gain by a metal-oxide-semiconductor transistor. The write/read operation for a selected cell within the array is demonstrated. The measured states are separated by /spl sim/1000 electrons for the 1 /spl mu/m/spl times/1 /spl mu/m memory node cell and by 60 electrons for the 1 /spl mu/m/spl times/70 nm memory node cell. Single-electron transistor controlled operation persists up to a temperature of 65 K.