A painless way to reduce power dissipation by over 18% in Booth-encoded carry-save array multipliers for DSP

A very simple reorganization of a Booth-encoded carry-save array multiplier is shown to reduce power dissipation in DSP applications. The proposed architecture, a rather straightforward rearrangement of the standard carry-save array, is particularly suitable for applications where one of the multiplier's input signals has a large dynamic range. We take advantage of the sign-extension zero-encoding property of a Booth encoder to reduce the total switching activity in the adder array, hence lowering the power dissipation. The proposed structure has been synthesized using Synopsys Design Compiler and the layout has been produced using Cadence Silicon Ensemble in a 0.5-/spl mu/m technology. The layout displays no penalty in circuit and routing area. Experimental results show that over 18% power reduction can be achieved when the proposed multiplier is used in a multiplexed FIR filter.