Hough transform algorithm for FPGA implementation

A novel algorithm for computing the Hough transform (HT) is introduced. The basic idea consists in using a combination of an incremental method with the usual HT expression to join circuit performance and accuracy requirements. The algorithm is primarily developed to fit field programmable gate arrays (FPGA) implementation that have become a competitive alternative for high performance digital signal processing applications. The induced architecture presents a high degree of regularity, making its VLSI implementation very straight forward. This implementation may be achieved by a generator program, assuring a shorter design cycle and a lower cost. For illustration, implementation results of an HT parameter extractor for 8-bit image pixels is given.