Efficient mapping of CORDIC algorithms on FPGA

This paper presents a study of the efficient mapping on FPGA of the operators required to implement redundant arithmetic based CORDIC algorithms. It is shown that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional ones. On the other hand, the speed advantages of the full-custom design has been lost, due to the longer routing delays caused by the increase of the fanout and the number of nets in the implementation of the redundant operators. Therefore, it is concluded that redundant arithmetic-based CORDIC methods are not suitable for implementation on FPGA.