Emitter resistance and performance tradeoff of submicrometer self-aligned double-polysilicon bipolar devices

The emitter resistance of polysilicon emitter bipolar transistors with an emitter area ranging from 0.6*2.4 mu m/sup 2/ to 3.4*10.4 mu m/sup 2/ has been characterized as a function of process parameters. The emitter polysilicon layer resistance plays a dominant role in determining the total emitter resistance of a small emitter area of 0.7*2.5 mu m/sup 2/, when the emitter diffusion is performed at 1000 degrees C. When the emitter diffusion temperature is reduced to 950 degrees C or below, the interfacial resistance between the n/sup +/-polysilicon and the n/sup +/-silicon layers starts to show a noticeable contribution to the total emitter resistance. An in situ emitter surface cleaning with HCl gas at 600 degrees C shows no effect on the emitter resistance, but results in a current gain reduction and an increase in the emitter saturation current. The emitter resistance increases almost two times when the emitter area is scaled from 1.2*3.0 mu m/sup 2/ to 0.7*2.5 mu m/sup 2/, while the cutoff frequency increases less that 6% and the ECL-gate delay time decreases less than 10%. Based on a SPICE simulation, an emitter resistance larger than 100 Omega starts to show a significant increase in ECL-gate delay time. It is concluded that it is better to maintain the emitter area as large as possible within an acceptable range of circuit design criteria to avoid the emitter resistance constraint for submicrometer double-polysilicon bipolar devices.<
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