Low-power skewed static logic (S/sup 2/L) with topology-dependent dual Vt

In this paper, we describe Skewed Static Logic (S/sup 2/L) with topology-dependent dual Vt which exhibits low-power, high-performance operation. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. The noise tolerance of proposed technique is presented with simulation results. We have designed NAND-NOR gate chains using 0.18 /spl mu/m CMOS technology and verified that S/sup 2/L reduces energy/spl times/delay over MS CMOS by 27-50%. We have also designed 32-bit carry-lookahead adders and verified that S/sup 2/L with dual Vt reduces delay by 43% and energy/spl times/delay by 31% over the conventional CMOS circuit for 1 V power supply.