High level estimation of the area and power consumption of on-chip interconnects

This paper addresses the problem of estimating the power and area consumption of on-chip interconnects for standard cell ASIC processes. We introduce a set of analytic investigations on buses, crossbar switches, and multiplexors. Furthermore, we prove the accuracy of the results by comparing them with gate-level power-estimations on a double metal 0.6 /spl mu/m CMOS technology.