An efficient method for estimating switching activity in arithmetic circuits using a lumped delay model

In this paper we present a method for efficiently estimating the switching activity for circuits prone to a high degree of toggle power by partitioning the circuit and using a lumped delay model to capture transitions along the critical path. This approach is best suited for arithmetic circuits due to their long critical path and is based on the observation that the low order bits will stabilize before the high order bits at the output. This approach offers up to an 85% savings in computational time and resources with a 17% increase in accuracy over the zero delay model for the circuits investigated.