A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power

This paper presents an inductor-less fractional-N clock multiplier with low integrated jitter and power. The architecture is based on a multiplying delay locked loop with a sub-sampling bang-bang phase detector and a novel digital-to-time converter (DTC) range-reduction technique which limits the jitter added to the reference signal, at no additional power penalty. The prototype, implemented in 65nm CMOS, covers the 1.6-to-3.0-GHz range and achieves an absolute RMS jitter (integrated from 30kHz to 30MHz) of 397fs at 2.5mW power consumption, leading to a jitter-power Figure of merit of -244dB. In-band fractional spurs are as low as -51.5dB and the occupied core area is 0.0275mm
²
.