A 3.3-mW Low Phase Noise VCDL for Factorial Delay-Locked Loops

A voltage-controlled delay line (VCDL) circuit to be used in factorial delay-locked loops (DLLs) that meets the requirements of the radio frequency (RF) communication standards in the band of 0.9-4 GHz is presented. The proposed circuit utilizes a differential ring oscillator with sub-feedback loops to obtain multi-phase outputs. A differential current-starved delay cell with symmetrical load is used. The circuit offers two quadrature phase outputs. The proposed VCDL achieves a very low phase noise of -143 dBc/Hz with a figure of merit of -208 dBc/Hz meeting the phase noise requirements of the GSM standard; the most severe standard in terms of phase noise requirements in the targeted band. The circuit consumes a 3.3-mW from a 1.2-V supply implemented in 130-nm CMOS technology and occupies an area of 66×40 μm2.