Parallel Viterbi algorithm for a VLIW DSP

The Viterbi decoder algorithm for a very high data-rate satellite receiver is computationally very intensive. Dedicated commercially available chips are used for high rate convolutional decoders. With the advent of high speed DSPs, these computationally intensive algorithms can be mapped on programmable DSPs running test of the receiver algorithm. This paper presents the Viterbi algorithm specially designed for VLIW DSPs and its implementation on a commercially available DSP for a very high data rate coherent burst demodulator satellite receiver.