A self-biased low voltage, low power, CMOS transconductor stage

A self-biased CMOS transconductor stage, able to work with a low-voltage supply and low-power dissipation, is proposed. A fully differential configuration in a 0.25 /spl mu/m minimum lithography technology has been utilized to design the circuit. Paying particular attention to the mismatch problems, a correct sizing of the circuit has been made. With a voltage supply of 1.2 V, the power consumption is 200 /spl mu/W and the gain bandwidth product is equal to 30 MHz. Utilizing the transconductor proposed here, a biquadratic cell has been simulated: imposing a central frequency of 1 MHz, the filter reaches 1% of THD with 275 mV peak differential sinusoidal input signal, while the total input noise is about 190 /spl mu/V/sub r.m.s./. With a power consumption of 1 mW, the cell presents a dynamic range of 60 dB and a SNDR peak of 48.6 dB.