FPGA Implementation of Asynchronous Mousetrap Pipelined Radix-2 CORDIC Algorithm

The COordinate Rotation DIgital Computer (CORDIC) is a special purpose algorithm to compute trigonometry functions. CORDIC has achieved attention of many researchers because of its simpler hardware. It uses shifter and adder only to perform the various functions which is used in real time applications such as Fast Fourier Transform (FFT) in communication and Discrete Cosine Transform in image processing. This paper aims at implementing the RADIX-2 CORDIC using asynchronous pipeline, to increase the throughput and to reduce the power. Further the detailed comparison between synchronous pipelined implementation and asynchronous pipelined implementation is presented. Four main parameters, throughput, power, Power-Delay Product (PDP) and cell utilization are considered for comparison. The design is implemented in Verilog HDL and synthesized for target device Artix-7 series FPGA. Simulation and analysis of routed design is performed and the obtained results demonstrate that the asynchronous implementation has 36.14% less power consumption, 16% high throughput and 44.94% improvement in Power Delay Product (PDP).