Spacer Effects on the Circuit Performance of DG Junctionless Transistor

In this paper, the spacer effects (both low and high-k) on the dc performance of n-type and p-type double gate junctionless transistor (DGJLT) has been investigated and presented. First, the dc characteristics of DGJLT has been studied for room temperature. Then the variation in the dc characteristics has been analyzed for different spacer materials. Finally, a CMOS inverter circuit has been designed andits performance is also studied. The simulation results shows that the introduction of spacer material enhances the inverter circuit performance.