Single level integrated packaging modules for high performance electronic systems

In this paper, we introduce a novel packaging scenario that aims to integrate or eliminate the existing multilevel packaging hierarchies towards single level integration. The new approach is actually an extension of VLSI technology where standard IC processes were pursued in the whole fabrication sequence. Test samples were made successfully. The module and interconnect structures, integration process, and electrical performance were studied theoretically and experimentally. Properties of signal propagation and coupling from chip to chip were simulated and measured in frequency domain as well as in time domain. It shows that off-chip communication with several Gb/s data rate is possible in such modules.