Noise verification across 3 levels of packaging hierarchy for the IBM G5/G6 mainframes

This paper describes the noise verification process across three levels of packaging for the IBM S/390 G5/G6 system. With over 11,000 critical nets in the system the design philosophy is founded on checking of noise magnitude on every net within the Central Electronics Complex (CEC). The CEC includes an MCM, the board, and memory cards. Description of the noise checking methodology as well as identifying nets exceeding the receiver noise immunity, the electrical characterization, geometrical extraction, transmission line effects, Delta-I calculations and statistical noise summation results will be presented.