Efficient and reusable time-sharing architectures for equalizer structures

Efficient and reusable time-sharing architectures are derived, that allow the implementation of a time-domain equalizer and similar functions. The fact that the clock rates in modern sub-/spl mu/m CMOS processes are much higher than the usually required sample rates can be exploited for a significant reduction of chip area. Special care is taken to preserve the known advantages of very efficient architectures like bitplane-based filter structures.