A noise-tolerant dynamic circuit design technique

A new circuit technique, referred to as the twin-transistor technique, for increasing the noise immunity of dynamic logic circuits is presented. This technique makes dynamic logic gates more tolerant to noise appearing at the gate inputs. A multiply-accumulate circuit has been designed and fabricated using a 0.35 /spl mu/m process to verify this technique. Experimental results indicate that the twin-transistor technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4 X) with only a modest increase in power dissipation (15%) and no loss in throughput.