A low-power CMOS super-regenerative receiver at 1 GHz

A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35 /spl mu/m CMOS process is described. The receiver includes a LNA, a super-regenerative oscillator, an envelope detector, AGC circuitry with sample/hold capability and a baseband amplifier. The die-surface is equal to 0.25 mm/sup 2/. An overall noise figure of 14.7 dB is achieved. The power consumption is less than 1.2 mW at V/sub DD/=1.5 V. A 100 kHz saw tooth quench signal has been used to achieve an interferer rejection of -35.9 dB at 500 kHz from the center frequency.