Low Power, and Highly Reliable Single Event Upset Immune Latch for Nanoscale CMOS Technologies

The susceptibility of sequential logic circuits to radiation induced soft errors is increasing as CMOS transistors are scaling down and the supply voltage is decreasing. Latch circuits are one of the main parts of sequential logic and can be affected by radiation. This paper proposes and evaluates a new highly reliable and low cost latch circuit capable of tolerating energetic particles. Employing a 45nm CMOS model, SPICE simulations reveal that the proposed latch can fully tolerate the radiation induced single event upsets (SEU) caused by high energetic particles. Moreover, the proposed SEU immune latch circuit has the lowest power consumption with respect to other recently proposed SEU tolerant latches. It is shown that up to 80% power saving is obtainable. Furthermore, the proposed circuit offers a lower delay and also a lower power delay product (PDP).