Failure Analysis of a Degraded 1.2 kV SiC MOSFET after Short Circuit at High Temperature

This paper presents the experimental results obtained from investigating the impact of short-circuit in SiC MOSFETs at high temperatures. The results indicate that a gate degradation mechanism occurs under a single-stress short circuit event at nominal voltage and junction temperature of 150° C. The failure mechanism is the gate breakdown, which can be early detected by monitoring the voltage drop of the gate-voltage waveform. The reduction of the gate voltage indicates that a leakage current flows through the gate, leading to a permanent damage of the device but preserving its voltage blocking capability. This hypothesis has been validated through semiconductor failure analysis by comparing the structure of a fresh and a degraded SiC MOSFET. A Focused Ion Beam cut is performed showing cracks between the poly-silicon gate and aluminium source. Furthermore alterations/particles near the source contact have been found for the degraded device.