Understanding PBTI in Replacement Metal Gate Ge n-Channel FETs With Ultrathin Al2O3 and GeOx ILs Using Ultrafast Charge Trap–Detrap Techniques

We report positive bias temperature instability data in replacement metal gate Ge n-channel metal- oxide-semiconductor field-effect transistors with an in-situ gate stack employing an ultrathin (5 Å), stable Al
₂
O
₃
interlayer (IL) using ultrafast (~microseconds) characterization techniques that ensure recovery artifactfree measurements. Comparison with state-of-the-art GeO
_x
IL is also reported besides establishing correlations between band-edge interface trap density (Dit), mobility (μ), and threshold voltage (VT) instability. Ultrafast measurestress-measure (UF-MSM), ultrafast measure-stress-detrapmeasure (UF-MSDM), stress-induced-leakage-current (SILC), direct-current current-voltage (DCIV), split capacitance-voltage (C-V), and low-temperature full conductance techniques along with a compact model demonstrate that: 1) trap generation occurs at IL/high-k interface during stress; 2) an increase in μ with reduction in Dit does not guarantee better reliability, i.e., V
_T
shift and μ are uncorrelated due to their dependence on separate regions of the gate stack; 3) contributions to total V
_T
degradation from trapping and generated traps are mutually exclusive; 4) UF-MSDM is a powerful tool to estimate trap generation; and 5) V
_T
degradation is directly proportional to high-k thickness, varies inversely with IL thickness, and reduces with annealing.