Improved synchronization methodologies for high performance digital systems

Traditional synchronization methodologies have largely concentrated on the use of a global clock signal to maximize the functional integration possible on the chip. Unfortunately, distribution of a low skew clock signal over the entire die at current clock rates is becoming increasingly difficult. By using a combination of architectural design and delay insensitive data encoding, it is possible to ameliorate the inter-patch penalties and take synchronization overhead into account. Extending this architectural modeling, it is also possible to account for other types of overhead, such as those due to Vdd changes between digital regions and analog or RF regions, thus enabling design optimizations for system on a chip applications. Finally, a potential methodology for containing metastability at synchronizer boundaries with relatively low latencies is proposed.