Data-flow Aware CNN Accelerator with Hybrid Wireless Interconnection

Deep convolution neural networks (CNNs) are computationally intensive machine learning algorithms with a large amount of data that impose various challenges for their hardware implementation. To meet the high computing demands of CNNs, many accelerator designs are proposed that revolve around achieving high parallelization, increasing on-chip data reuse and efficient memory hierarchy, etc. However, very few works have attempted to address the communication challenges in these massively parallel accelerators architectures, which is the most anticipated performance bottleneck. Traditional interconnections like bus, crossbar and even Network-on-Chip ( N o C) topologies like mesh fail to achieve the peak performance required by the large number of processing elements on accelerators. In this work, we address the communication bottlenecks of accelerators by extensively studying the application data-flow. We propose an efficient accelerator architecture that employs broadcast enabled low latency wireless links along with traditional wired links to efficiently support the data-flow of accelerators and achieve high communication performance. Evaluation of the proposed design shows that it achieves 28 % latency reduction, 19x bandwidth improvement and 35% network energy saving as compared to baseline wired networks.