Design automation in a subwavelength world

Have we reached the end of the traditional circuit design process, which assumes layout equals mask equals silicon? As the relationship between layout and what appears on the wafer becomes increasingly complex and unpredictable, how will EDA design and verification flows change? Will we have lithography simulators inside layout tools? Must the scope of EDA grow to encompass mask manufacture and inspection issues? Will the individual polygon, in its unique context, become the first-class citizen of future design methodologies, lowering the level of abstraction even as chip complexity skyrockets?