Electrical analysis of InGaAs-based planar and tri-gate nMOSFET with S/D resistance dependencies at different drain biases

This paper studies the electrical analysis of InGaAs-based planar and tri-gate nMOSFET and the influence of the source/drain (S/D) resistance, R
_sd
on the current-voltage (I
_d
-V
_g
) relation at different drain biases (V
_ds
). It is found that the tri-gate nMOSFET simulated at high V
_ds
has shown better performance compared to planar nMOSFET simulated at low V
_ds
. As the R
_sd
is reduced, the drain current of both planar and tri-gate devices increases. The on-current to off-current (I
_on
/I
_off
) ratio of the devices also increases as the Rsd reduced. Tri-gate nMOSFET shows significant improvement as the Ion/Ioff ratio is 103 higher than the planar nMOSFET device.