On the origin of the dispersion of erased threshold voltages in flash EEPROM memory cells

This work investigates the origin of the dispersion of tunnel-erased threshold voltages (V/sub T/) in flash EEPROM memory cells. A clear correlation between cell-to-cell variations of tunnel current I/sub T/ and dispersion of erased V/sub T/ is demonstrated by looking at the I/sub T/ characteristics and the erasing characteristics corresponding to channel and source injection as well as at the dependence of I/sub T/ and V/sub T/ dispersion on device area and tunnel polarity. Experimental evidence is provided that nonuniform injection at poly-Si/SiO/sub 2/ interface is a major cause of erased V/sub T/ dispersion.