Combined pseudo-exhaustive and deterministic testing of array multipliers

The paper presents a new method for bit-parallel testing of array multipliers using a novel approach of data-controlled segmentation of the circuit to transform the task of testing 2-dimensional arrays to the task of testing a set of 1-dimensional arrays. Pseudo-exhaustive and deterministic testing are combined to achieve high coverage of a broad class of gate-level faults. The well-structured test sequences can be implemented both, as a software or hardware based BIST. Experiments demonstrate the advantages of the new approach compared with state-of-the-art methods.