Challenges resulting from the use of spark gaps for superimposed voltage tests

Suitable testing techniques are required to ensure reliable operation of novel HVDC equipment. For instance, HVDC cables and their accessories as well as HVDC GIS/GIL are required to undergo a superimposed voltage test where the test object is stressed simultaneously with a DC voltage and an impulse voltage (LI/SI). In this respect the mutual influence of the voltage generators needs to be considered. Usually a blocking spark gap or a blocking capacitor is used to protect the impulse generator from DC stress. While there are no major challenges associated with the latter, spark gaps oftentimes cause deviations of the standardized voltage waveforms. Depending on the type of impulse voltage the impulse's front, tail or even both can be distorted heavily which will be illustrated in this contribution. Additionally, the underlying phenomena will be discussed.