A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro

0.18 /spl mu/m logic process technologies have recently been used to develop a loadless CMOS four-transistor SRAM cell (4T-cell) whose size (1.934 /spl mu/m/sup 2/) is only 56% that of a conventional six-transistor SRAM cell (6T-cell). Using this 4T-cell technology. The authors present a 16 Mb, 400 MHz SRAM macro which features: (1) an end-point dual-pulse driver (EDD) for stable data hold and minimum cycle time, (2) word-line-voltage-level compensation (WLC) for stable static data hold, and (3) an all-adjoining twist bit-line (ATBL) to reduce bit-line coupling capacitance.